Design of a 1-chip IBM-3270 protocol handler

The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4 manweeks. The design methodology stresses the application of high-level silicon constructs and built-in testability

VLSI top-down design based on the separation of hierarchies

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified by an experimental self-timed CMOS RISC computer design

A knowledge-based approach to VLSI-design in an open CAD-environment

A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI technique can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge - strategic and task-specific - in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design

Process identification through modular neural networks and rule extraction

Monolithic neural networks may be trained from measured data to establish knowledge about the process. Unfortunately, this knowledge is not guaranteed to be found and - if at all - hard to extract. Modular neural networks are better suited for this purpose. Domain-ordered by topology, rule extraction is performed module by module. This has all the benefits of a divide-and-conquer method and opens the way to structured design. This paper discusses a next step in this direction by illustrating the potential of base functions to design the neural model. \ud [Full paper published as: Berend Jan van der Zwaag, Kees Slump, and Lambert Spaanenburg. Process identification through modular neural networks and rule extraction. In Proceedings FLINS-2002, Ghent, Belgium, 16-18 Sept. 2002.

Analysis of Neural Networks through Base Functions

Problem statement. Despite their success-story, neural networks have one major disadvantage compared to other techniques: the inability to explain comprehensively how a trained neural network reaches its output; neural networks are not only (incorrectly) seen as a "magic tool" but possibly even more as a mysterious "black box" [1]. This is an important aspect of the functionality of any technology, as users will be interested in "how it works" before trusting it completely. Although much research has already been done to "open the box," there is a notable hiatus in known publications on analysis of neural networks. So far, mainly sensitivity analysis and rule extraction methods have been used to analyze neural networks. However, these can only be applied in a limited subset of the problem domains where neural network solutions are encountered

Molding the Knowledge in Modular Neural Networks

Problem description. The learning of monolithic neural networks becomes harder with growing network size. Likewise the knowledge obtained while learning becomes harder to extract. Such disadvantages are caused by a lack of internal structure, that by its presence would reduce the degrees of freedom in evolving to a training target. A suitable internal structure with respect to modular network construction as well as to nodal discrimination is required. Details on the grouping and selection of nodes can sometimes be concluded from the characteristics of the application area; otherwise a comprehensive search within the solution space is necessary

MOD/R : A knowledge assisted approach towards top-down only CMOS VLSI design

MOD/R models all views on the design space in relations. This is achieved by eliminating the package constraints, as are apparent in PCB oriented hardware description languages. Assisted by knowledge engineering it allows for a top-down, mostly hierarchical decomposition, virtually eliminating the need for bottom-up assembly